1. Field of the Invention
The present invention relates to programmable logic arrays (PLAs). More specifically, the present invention relates to address transition detectors used in programmable array logic (PAL) circuits.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Programmable logic arrays provide `glue logic` for PC (printed circuit) boards and provide other types of PC board logic. Glue logic is the logic required to interface two PC boards and to interface other PC board circuitry. Glue logic generally includes a plurality of AND gates, OR gates and input/output (I/O) buffers. PLAs may also contain other logic elements including registers and flip-flops. PLAs consume less space and therefore generally provide circuit logic in a less costly manner than individual logic gates.
PLAs also offer the advantage of reconfigurability over discrete or individual gates. That is, PLAs generally include an array of AND gates, an array of OR gates, and some provision for interconnecting the outputs of selected AND gates to the inputs of selected OR gates. PLAs allow a wide variety of logic functions to be implemented through the combination, via the OR gates, of the product terms provided by the AND gates. Further, the configuration of the array may be quickly, easily and relatively inexpensively reprogrammed to implement other functions.
As described in U.S. Pat. No. 4,124,899, programmable array logic (PAL) circuits were developed to provide further improvements in the speed, space requirements, cost and power consumption of PLAs. PALs generally provide programmable AND and fixed OR functions. In a most general sense, a PAL provides a field programmable logic array in which a programmable array of circuit inputs are provided to a plurality of AND gates (cells) to generate product terms. Outputs from subgroups of AND gates are, in turn, nonprogrammably connected as inputs to individual, specified OR gates to provide the sum of products. In many cases, PALs also include other types of logic elements.
PALs are often used in applications where power consumption must be limited. That is, low power consumption of PALs may extend the operating life of battery operated circuits such as that of laptop computers and cellular phones. In addition, reduced PC board power consumption allows for smaller and less expensive power supplies, reduced system cooling requirements and, thus, reduced overall package size.
Many conventional PALs use address transition detectors to turn off subcircuits when the PAL inputs are at a steady-state, thus reducing the power consumption of the device. The detectors turn off circuitry when the
is at steady-state and then turn the PAL circuitry back on when a transition is made on any of the PAL inputs.
Typical address transition detectors utilize exclusive-NOR gates. Exclusive-NOR address transition detectors generally have a high device count and therefore tend to require considerable die surface area. Further, circuit design to achieve a particular pulse width for the transition detection signal is difficult.
Thus, there is a need in the art for an address transition detector for PAL circuits that requires less die surface area, is easy to implement and provides a controllable transition detection signal.